1. Field of the Invention
This invention relates to an improved built-in system for testing integrated circuits, and more particularly to a built-in array test system that is programmable.
2. Description of the Prior Art
In general, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well-known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This so-called Array Built-In Self Test (ABIST) technology allows high speed testing of the array without having to force correspondence between the array and the input/output connections to the chip itself. In order to provide high speed testing and to confine the test system to a minimum area of the chip, prior art ABIST systems (test patterns, control sequences, test data gathering) are hardwired systems specifically designed to test for particular types of errors predicted to occur in the array. This necessitates chip logic changes if/when new self test functions or features become required (as, for example, in the case that a previously unexpected failure mechanism must now be tested for). Also, test patterns have generally been limited to a well-known set including all 0's, all 1's, checkerboard, checkerboard complement, and pseudo-random. These prior art systems permit very limited looping and "address hold" test capabilities, and addressing controls typically allow only one type of change (increment or decrement, for example) per test sequence.
U.S. Pat. No. 5,173,906 to Dreibelbis et al, issued Dec. 22, 1992, provides a BIST (Built-In Self Test) function for VLSI logic or memory module which is programmable. This circuitry is provided with a looping capability to enable enhanced burn-in testing. An on-chip test arrangement for VLSI circuits is provided with programmable data pattern sequences wherein the data patterns are selectable via instruction code in order to reduce the probability of self test redesign. However, this Dreibelbis patent does not provide flexibility to test VLSI circuits with any and all tests which can be required to test both static and dynamic arrays.